Manufacturers of semiconductors regard testing and evaluation processes as ubiquitous and indispensable to design and production operations. Semiconductors, also known as integrated circuits (I.C.) and computer chips, are tiny electronic circuits etched on silicon that electronically process, store and move information. As broadly discussed below, processes associated with semiconductor production involve substantial investment of economic and manpower resources. Consequently, it is advantageous to verify I.C. layout integrity prior to committing a design to silicon.
Manufacturers create an integrated circuit on the surface of a doped, polished silicon wafer. Production processes may employ diffusion, thin films, oxidation, photolithography, deposition and/or etching techniques to apply a first microscopic layer to the wafer. Designers configure multiple layers of polysilicon, silicon oxide, silicon nitride and metal to form a unique structure responsive to intended application and desired electrical characteristics.
During a masking phase, a chip manufacturer delineates microscopic paths operable to carry electronic impulses throughout the semiconductor. More particularly, masking processes apply a light sensitive resist substance to the wafer. Manufacturers position a detailed mask of thousands of individual semiconductor circuits over the surface, and project lights onto the wafer. Surfaces left exposed by the mask are altered by the light, and a chemical wash reveals a new mask layer on the wafer. The process repeats for each desired layer, resulting in elaborate, miniaturized circuitry.
An I.C. design file drives the masking processes. Program code within the file describes and defines mask parameters and specifications as read by the production equipment. Conventional formats for such files include Graphic Design System (GDS) and Caltech Intermediate Format (CIF). Design files comprise, in part, sequences of cell descriptions. Cells may be viewed as preprogrammed logical units that perform a distinct function. For instance, individual cells may comprise investors, capacitors, gates, oscillators and/or multiplexors. As such, the standard cells may be incorporated into multiple semiconductor designs. When incorporated into a file layout, design engineers integrate these individual cells with others to form a chip layer.
Parent libraries store individual cells along with others grouped by version or designer preference. In this manner, the libraries may act as a template or pallette from which designers may retrieve and apply component cells. As such, libraries make cells available for automatic placement and routing within a custom semiconductor layout. In practice, designers may use default cells from a most recent library version to populate I.C. design files. Other applications may require proprietary cells from more dated, particular libraries.
Once the masked layers are in place, manufacturers use diamond saws to section hundreds of chips from the wafer. The chip may then be encased in a plastic or ceramic shell with exposed connectors. The completed product may be tested once more and put through a “burn-in” or trial use process. Packaged chips that pass this final rigorous test are then installed into circuit boards and consumer products. Defective chips are discarded at a loss to the manufacturer.
Due to the complexities and costs inherent to the above manufacturing processes, it is extremely advantageous to detect errors prior to mask creation and application. However, typical I.C. design files may be marred with multiple instances of corruption. For example, faulty or otherwise obsolete cells may be erroneously incorporated or retained within a file. Left undiscovered, the inappropriate and broken processes borne of theses cells can propagate to production, ultimately translating into wasted resources. Additionally, other processes require identification of specific cells of interest, including those associated with license fees, unauthorized modifications and resource development.
Yet, in contrast to the highly automated environment responsible for chip layering, layout designers often must resort to manual evaluation of files prior to production. This labor and time intensive process tolerates error and inefficiency. Consequently, what is needed is an automated, efficient manner of identifying potentially, problematic cell structures within an I.C. design file.